NVIDIA H100 specifications ↗
SXM and NVL specifications; memory is per GPU
HTML · Source reviewed 2026-09-08 · Opens at the manufacturer
Manufacturer documents used in our exact-variant references. Check the product, revision and footnotes before applying a specification to an offer.
36 source records · Files open at the original publisher. Source availability and revisions can change.
SXM and NVL specifications; memory is per GPU
HTML · Source reviewed 2026-09-08 · Opens at the manufacturer
Confirms H100 SXM5 HBM3 and PCIe HBM2e
HTML · Source reviewed 2026-09-08 · Opens at the manufacturer
Document identifies itself PB-11133-001_v02. Table 6 gives 600 GB/s NVLink; introduction says 900 GB/s. Table 6 used
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Per-card identity and bridge topology
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Resolved from NVIDIA resource portal
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Manufacturer labels specification table preliminary
HTML · Source reviewed 2026-09-08 · Opens at the manufacturer
Resolved from manufacturer product page
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Confirms no NVLink or MIG
HTML · Source reviewed 2026-09-08 · Opens at the manufacturer
80GB PCIe and SXM; CTS power footnote
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Current linked datasheet
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
PB-10137-001_v03; memory table and board power
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Pages 35-37 document original A100 40GB SXM4
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Manufacturer specifications; historical publication does not establish current software qualification
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Manufacturer specifications; historical publication does not establish current software qualification
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Manufacturer specifications; historical publication does not establish current software qualification
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Manufacturer specifications; historical publication does not establish current software qualification
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
January 2020 table separates V100 PCIe, V100 SXM2 and V100S; no V100S specifications transferred to V100
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Pre-Turing offline compilation removal in CUDA 13; legacy deployment qualification needed
HTML · Source reviewed 2026-09-08 · Opens at the manufacturer
Corroborates memory, bandwidth, 300W rating, passive cooling and dimensions
HTML · Source reviewed 2026-09-08 · Opens at the manufacturer
January 2023 v03 marked preliminary; physical card figure on printed page 1, dimension drawing printed page 11
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Table 1 explicitly separates per-GPU and per-node memory/bandwidth; unrelated CPU table cells contain apparent editorial errors and are not used
HTML · Source reviewed 2026-09-08 · Opens at the manufacturer
Page 1 explicitly states individual GPU maximum configurable power and SXM6; platform performance and weight are not per-GPU fields
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
An example power-limit response is not treated as a universal B300 TDP specification
HTML · Source reviewed 2026-09-08 · Opens at the manufacturer
Page 1 explicit shared compute rows for PCIe/SXM 40GB/80GB with separately printed dense and sparse values
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
September 28 2023 body explicitly states PCIe vector FP32/FP64 and tensor FP64 peaks; benchmark results and ambiguously qualified BF16 headline are not reused
HTML · Source reviewed 2026-09-08 · Opens at the manufacturer
Infinity Fabric bandwidth is per link; eight links listed
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Manufacturer linked two-page datasheet
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Peak board power, not measured system consumption
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Manufacturer linked two-page datasheet
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Reference geometry on page 1; three links are per-card capabilities, not a complete-server topology
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Per-accelerator memory, interface and typical board power
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Per-accelerator memory, interface and typical board power
HTML · Source reviewed 2026-09-08 · Opens at the manufacturer
Printed page 15 distinguishes air-cooled MI350X and direct-liquid-cooled MI355X platform configurations
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Page 1 explicitly labels maximum TBP and specifies seven scale-up links at 153.6 GB/s each. Product webpage uses typical board power terminology.
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Page 1 explicitly labels maximum TBP and specifies seven scale-up links at 153.6 GB/s each. Product webpage uses typical board power terminology.
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
Pages 9, 18 and 22 distinguish OAM from HL-338 PCIe
PDF · Source reviewed 2026-09-08 · Opens at the manufacturer
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